FIG. 1 is a diagram showing a process of a method for manufacturing a thin film transistor (TFT) having an etch stop layer (ESL) in the related art. The method includes:
Step S11, forming a gate electrode 102 and a gate insulating layer 103;
Step S12, forming a pattern of an active layer 104 on the gate insulating layer 103 by using a single patterning process;
Step S12 may specifically include: forming a metal oxide semiconductor thin film on the gate insulating layer 103; then coating a photoresist on the metal oxide semiconductor thin film; next, exposing and developing the photoresist to form the pattern of the active layer 104; and then peeling off the remained photoresist;
Step S13, forming a pattern of an ESL 105 on the active layer 104 by using a single patterning process;
Step S13 may specifically include: forming an ESL thin film on the active layer 104; then coating a photoresist on the ESL thin film; next, exposing and developing the photoresist to form the pattern of the ESL 105; and then peeling off the remained photoresist;
Step S14, forming two contact holes 106 which are configured to connect the active layer 104 and a source electrode/drain electrode formed subsequently, on the ESL 105;
Step S15, forming the source electrode 107 and the drain electrode 108 having an interval L therebetween on the ESL 105 by using a single patterning process.
FIG. 2 is a diagram showing a structure of an oxide TFT prepared by the method as shown in FIG. 1.
An interval L0 between the two contact holes 106 is referred to a channel length of a TFT. When the interval between the two contact holes 106 is arranged, an overlay tolerance between the contact holes 106 and the source electrode 107/the drain electrode 108 as well as a resolution error of a photo process need to be considered. In other words, a resolution error of a common exposure machine (typically 4 μm), a design length (typically 3 μm) and an overlay tolerance (typically 3 μm) need to be considered. At this circumstance, the channel length L0 is of about 10 μm, which is about 2.5 times of a channel length of a back channel etching (BCE) type TFT. A large channel length is one of the major causes of lowering the performance of a TFT.